The semiconductor device industry has a market driven need to reduce the size of devices such as transistors, capacitors and electrically conductive interconnects. Smaller transistors result in improved operational speed and clock rate, and reduced power requirements in both the standby and operational modes. Smaller devices also need thinner dielectric layers, thinner diffusion layers and thinner conductive interconnect layers. Thinner conductor layers may result in what are known as step coverage issues when the thin conductor lines traverse a steep contact step or edge. These steps or edges are becoming increasingly deep and narrow. The contact edges may be substantially deeper than the diameter of the contact hole, a situation known as a high aspect ratio contact hole, which may also cause step coverage and contact filling issues. Thinner layers may also be more sensitive to intermingling or diffusion of the different materials into regions where they may cause potential reliability problems. The increasingly small and reliable integrated circuits (ICs) will likely be used in products such as processor chips, mobile telephones, and memory devices such as dynamic random access memories (DRAMs). One known method of improving conductor reliability is the use of a layer of conductive titanium nitride (TiN) under, or over, other conductors, such as aluminum or copper in order to prevent the metal from diffusing into surrounding insulator layers. The deposition of TiN by means of chemical vapor deposition (CVD) or physical vapor deposition (PVD) methods such as sputtering, often results in layers with poor conductivity with CVD, usually expressed in terms of resistivity in units of ohm-cm, or in μohm-cm, or in poor conformality with PVD resulting in incomplete coverage.